Clock distribution networks are key elements of digital semiconductor devices. Clock signals are used to synchronize the operations performed in these devices and are typically distributed to thousands of clocked elements in the design. The characteristics of the clock waveform (for example, rise times of the clock edges, peak amplitude attained by the clock waveform, distance from power/ground rails, etc.) are critical to the overall performance of the device, as they determine the speed at which the clocked storage elements store data or propagate data to their outputs. As a consequence, significant design effort is expended on clock distribution networks, to ensure that clock waveforms conform to their specified characteristics. Furthermore, clock distribution networks tend to be significant sources of energy consumption in high-performance designs, as they usually include over-sized devices to ensure that they conform to their specified characteristics under all anticipated variations of fabrication and operational conditions. Consequently, in designs where it is desirable to minimize energy consumption, the design of clock distribution networks is especially challenging, because reductions in energy consumption of the clock distribution network will tend to negatively impact the ability of the clock distribution network to attain its specified characteristics.
Traditionally, a clock distribution network comprises a number of clock buffers that are used to propagate a reference clock signal from a single root point to multiple clocked storage elements. These clock buffers are supplied with power from the same power supply grid as the other circuitry in the device, and therefore, they operate at the same voltage level as the other circuitry. The arrival times of the clock signal to the storage elements are controlled by a variety of means, but generally at least in part by sizing the buffers so that the propagation delays of the various paths from the root to the storage elements are approximately equal. In addition to controlling the propagation delays of paths from the root to the storage elements, however, the sizing of the individual buffers is used to control the rise times of the clock signals as they are seen by the storage elements. In particular, the sizes of the buffers are typically made large enough to insure that the rise times and fall times of these clock signals cannot exceed a certain upper bound, because many types of storage elements will not attain their specified performance characteristics if the rise and/or fall times are too long.
In addition to the network of buffers, the system that supplies power to the buffers must also be considered as part of the overall clock distribution system. In most devices, the reference clock is distributed across the design to a set of final clock buffers, whose elements drive bufferless all-metal networks that deliver a clock signal directly to the inputs of storage elements; i.e., the last stage of buffers in the distribution network. These final buffers are typically large and draw large amounts of current within a relatively small window of time. These large current draws over a small time window can overwhelm the ability of the device's power-supply system, and cause variations in the voltage supplied to the final drivers, negatively impacting their performance. Moreover, since the final drivers typically share the power-supply system with other parts of the overall device, any variations in voltage that they cause will affect the operation of other parts of the device, and have additional negative impacts. As a consequence, ensuring that components of the clock-distribution network receive a stable power voltage, and in addition, ensuring that these components do not compromise the power voltage supplied to other parts of the overall device is an important part of the clock distribution network design effort.
Energy consumption in clock distribution networks can generally be reduced with the same methods as other circuitry in a design. For example, the energy consumption of other circuitry can be reduced by reducing the voltage of the power supplied to the circuitry. Similarly, by reducing the voltage supplied to the buffers in the clock distribution network, the energy consumption of the network can be reduced as well. Energy consumption of other circuitry can also be reduced by using smaller transistors to implement the circuitry, and similarly, by reducing the sizes of the transistors that implement the buffers of the clock distribution network, energy consumption of the clock distribution network can be reduced as well. Unfortunately, reduction of the voltage supplied to the clock distribution network buffers and reduction of the sizes of the transistors used to implement the buffers will have a negative impact on the ability of the network to realize suitable rise and/or fall times. Longer rise and/or fall times will generally have a negative impact on the performance of the storage elements that use the clock signal. Moreover, since a reduction in the power-voltage supplied to the buffers will typically directly translate into a reduction in the peak-to-peak “swing” of the voltage of the clock signal itself, the performance of the storage elements that use the clock signal will further be negatively impacted.
Given the sometimes large amount of energy consumed by clock distribution networks, and the secondary impact of their performance on the performance of the various storage elements in a device, it can be desirable to be able to control the operation of the clock distribution network independently from the operation of the other parts of a device. For example, in some contexts, it can be desirable to operate other parts of a device with a very low power-voltage supply, in order to drastically reduce energy consumption. However, if the clock buffers are on the same supply grid as the other circuitry in the device, the peak-to-peak voltage swing of the clock signal and rise and/or fall times of the clock signal may be so compromised by the low power-voltage, that performance of the storage elements using the clock will be too poor to be practical. In a situation such as this, it would be desirable to decouple the supply of the clock distribution network from the supply of other circuitry by dedicating to it a separate supply grid. Such a separate supply grid would traditionally need to be distributed across the entire design, however, due to the distributed nature of the buffers in the distribution network, and thus, represents an amount of additional metal-interconnection resources that is not practical in many designs.
Resonant clock distribution networks have been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance.
Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 1 GHz filter with distributed resonant clock generator,” by Sathe V., et al., IEEE Symposium on VLSI Circuits, June 2007; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007; “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. Throughout these articles, driver sizing and duty cycle adjustment are used to minimize the amount of energy required to keep the resonant clock network swinging at the peak-to-peak power-voltage that would be realized by a traditional clock distribution network of buffers.
A hitherto unexploited characteristic of resonant clock distribution networks is that sizing of the resonant clock drivers and/or adjustment of the duty cycle of the reference clock will have an effect on the amplitude of the clock signal, without requiring the distribution of a separate voltage supply level. Consequently, by adjusting the size of the resonant clock drivers or the duty cycle of the reference clock in resonant clock networks, peak-to-peak clock levels can be made to be higher or lower than the voltage supplied to the other circuitry in the device, enabling higher performance at a given supply level, or higher energy efficiency at a given performance level. Specifically, for a given supply level, it is possible to operate the clock at a higher peak level, resulting in faster operation of the clocked storage elements and, therefore, faster operation of the device. Similarly, for a target performance level, it is possible to run the clock at a higher amplitude than the voltage supplied to the other circuitry, resulting in faster operation of the clocked storage elements, and thus, enabling further reduction in the voltage supply of the other circuitry. Moreover, unlike the distributed locations of clock buffers traditionally seen in non-resonant clock distribution networks, the locations of clock drivers in resonant clock distribution networks can be centralized at the locations of the requisite inductor elements, thereby avoiding the need for distributed-control solutions for the dynamic adjustment of clock driver sizing and/or duty-cycle of the reference clock.
In all prior art references, driver sizing and duty cycle adjustment are explored in the limited context of energy efficiency in the resonant clock network itself. They are not used to control clock rise and/or fall times or clock amplitude. Moreover, they are not used to impact overall power consumption in the device by operating the clock signal at a higher or lower voltage than the other circuitry in the device, with the objective of achieving higher performance at a target voltage level, or lower energy consumption at a target performance level.
Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.